As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as an FPGA, has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections are made between them. Such a stacked arrangement is referred to as a system-in-package (SIP).
Through die vias (TDVs) can be employed to establish interconnections between stacked ICs (also referred to as through silicon vias (TSVs)). A TDV is a metal via that extends through a die of one IC for coupling to interconnect of another IC. In the design of stacking-friendly ICs, regions in the device layout are dedicated to TDVs. In a typical stacked arrangement, a “daughter” IC is mounted on a “mother” IC. Depending on the source of the daughter IC, the die stacking-related integration (e.g., TDV formation, micro-bumping, and bonding) can be implemented either in the fabrication house (e.g., mother and/or daughter IC manufacturer) or in the assembly house (e.g., a separate facility for mounting a previously manufactured daughter IC to a previously manufactured mother IC). Typically, the manufacturing capabilities for TDV formation (e.g., density, diameter, pitch, aspect ratio, etc.) in the fabrication house differ than those of the assembly house. Further, the daughter IC may have various inter-chip interface densities. As a result, the mother IC has to physically and functionally support different TDV and micro-bump configurations based on the particular inter-chip interface of the daughter IC and the manufacturing capabilities of the fabrication/assembly process. Re-designing the mother IC for different daughter ICs and/or different manufacturing processes is time-consuming and expensive.
Accordingly, there exists a need in the art for a stacking-friendly IC implementation that can be used for various daughter IC and manufacturing configurations.